View GS8170S18_6589332.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev: 1.01 11/2000 1/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 1m x 18, 512k x 36 , 256k x 72 16mb synchronous sram 333 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 209-bump bga commercial temp industrial temp s ram features ? user-configurable early, late, and double late write modes ? user-configurable pipelined and flow through operation ? observes the sigma ram pinout standard ? 1.8 v +150/?100 mv core power supply ? 1.5 v or 1.8 v i/o supply ? dual cycle deselect in pipeline mode ? burst synchronous operation ? fully coherent read and write pipelines ? echo clock outputs track data output drivers in pipeline mode ? zq mode pin for user-selectable output drive strength ? byte write operation (9-bit bytes) in ew, lw, and dlw modes ? 2 user programmable chip enable inputs for easy depth expansion. ? ieee 1149.1 jtag-compatible boundary scan ? 209-bump, 14 mm x 22 mm, 1 mm bump pitch bga package ? pin compatible with future 32m, 64m, and 128m devices sigma ram family overview the gs8170 s 18/36 /72 b s s rams are built in compliance with the sigma ram pinout standard for synchronous srams. they are 18,874,368-bit (16mb) srams. these are the first in a family of wide, very low voltage cmos i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. gsi's s rams are offered in a number of configurations that emulate other synchronous srams, such as burst rams, nbt rams, late write, or double data rate (ddr) srams. the logical differences between the protocols employed by these rams hinge mainly on various combinations of address bursting, output data registering and write cueing. s rams allow a user to implement the interface protocol best suited to the task at hand. functional description because a sigma ram is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. output enable is the only asynchronous control input. output enable can be used to override the synchronous control of the output drivers and turn the ram's output drivers off at any time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation required by asynchronous srams and simplifies input signal timing. a s ram may be configured by the user to read in pipeline or flow through mode. in pipeline mode, an ordinary single data rate ram incorporates a rising-edge-riggered output register. for read cycles, a pipelined sram?s output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. gs817x18/36/72b s rams are implemented with gsi's high performance cmos technology and are packaged in a 209- bump bga. - 333 pipeline mode tkhkh 3.0 ns tkhqv 1.5 ns flow through mode tkhkh 7 ns tkhqv 5 ns 209-bump, 14 mm x 22 mm bga 1 mm bump pitch, 11 x 19 bump array bottom view
rev: 1.01 11/2000 2/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 8170s72 pinout 256k x 72 common i/o?top view 1 2 3 4 5 6 7 8 9 10 11 a dqg dqg a e2 a (16m) adv a (8m) e3 a dqb dqb b dqg dqg bc bg nc w a bb bf dqb dqb c dqg dqg bh bd nc (128m) e1 nc be ba dqb dqb d dqg dqg v ss nc nc g nc nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc v ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss ep3 v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd m4 v dd v ddq v ddq dqf dqf k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l dqh dqh v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss m3 v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc mcl nc nc v ss dqe dqe u dqd dqd nc a nc (64m) a nc (32m) a nc dqe dqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe ? 2000.02.18 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.01 11/2000 3/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 8170 s 36 pinout 512k x 36 common i/o?top view 1 2 3 4 5 6 7 8 9 10 11 a nc nc a e2 a (16m) adv a e3 a dqb dqb b nc nc bc nc a w a bb nc dqb dqb c nc nc nc bd nc (128m) e1 nc nc ba dqb dqb d nc nc v ss nc nc g nc nc v ss dqb dqb e nc dqpc v ddq v ddq v dd v dd v dd v ddq v ddq nc dqpb f dqc dqc v ss v ss v ss zq v ss v ss v ss nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc v ss v ss v ss ep3 v ss v ss v ss nc nc j dqc dqc v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l nc nc v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss m3 v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqpd nc v ddq v ddq v dd v dd v dd v ddq v ddq dqpa nc t dqd dqd v ss nc nc mcl nc nc v ss nc nc u dqd dqd nc a nc (64m) a nc (32m) a nc nc nc v dqd dqd a a a a1 a a a nc nc w dqd dqd tms tdi a a0 a tdo tck nc nc ? 2000.02.18 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.01 11/2000 4/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 8170 s 18 pinout 1m x 18 common i/o?top view 1 2 3 4 5 6 7 8 9 10 11 a nc nc a e2 a (16m) adv a e3 a nc nc b nc nc bb nc a w a nc nc nc nc c nc nc nc nc nc (128m) e1 a nc ba nc nc d nc nc v ss nc nc g nc nc v ss nc nc e nc dqpb v ddq v ddq v dd v dd v dd v ddq v ddq nc nc f dqb dqb v ss v ss v ss zq v ss v ss v ss nc nc g dqb dqb v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqb dqb v ss v ss v ss ep3 v ss v ss v ss nc nc j dqb dqb v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l nc nc v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss m3 v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r nc nc v ddq v ddq v dd v dd v dd v ddq v ddq dqpa nc t nc nc v ss nc nc mcl nc nc v ss nc nc u nc nc nc a nc (64m) a nc (32m) a nc nc nc v nc nc a a a a1 a a a nc nc w nc nc tms tdi a a0 a tdo tck nc nc ? 2000.02.18 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch
rev: 1.01 11/2000 5/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 pin description table pin location symbol description type comments a3, a5, a7, b7, u4, u6, u8, v3, v4, v5, v6, v7, v8, v9, w5, w6, w7 a address input ? c7 a address input x18 version only b5 a address input x18 and x36 versions a6 adv advance input active high b3, c9 bx byte write enable input active low (all versions) b8, c4 bx byte write enable input active low (x36 and x72 version s ) b4, b9, c3, c8 bx byte write enable input active low (x72 version only) k3 ck clock input active high k1, k11 cq echo clock output active high k2, k10 cq echo clock output active low e2, f1, f2, g1, g2, h1, h2, j1, j2, l10, l11, m10, m11, n10, n11, p10, p11, r10 dq data i/o input/output x18 , x36 , and x72 versions a10, a11, b10, b11, c10, c11, d10, d11, e11, r1, t1, t2, u1, u2, v1, v2, w1, w2 dq data i/o input/output x36 and x72 version s a1, a2, b1, b2, c1, c2, d1, d2, e1, e10, f10, f11, g10, g11, h10, h11, j10, j11, l1, l2, m1, m2, n1, n2, p1, p2, r2, r11, t10, t11, u10, u11, v10, v11, w10, w11 dq data i/o input/output x72 version only c6 e1 chip enable input active low a4, a8 e2 & e3 chip enable input programmable active high or low g6, h6 ep2 & ep3 chip enable program pin input ? d6 g asynchronous output enable input active low w9 tck test clock input active high w4 tdi test data in input ? w8 tdo test data out output ? w3 tms test mode select input ? l6, m6, j6 m2, m3 & m4 mode control pins input ? n6 mch must connect high input active high k6, p6, t6 mcl must connect low input active low
rev: 1.01 11/2000 6/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 background the central characteristics of the gsi s rams are that they are extremely fast and consume very little power. because both operating and interface power is low, s rams can be implemented in a wide ( x72 ) configuration, providing very high single package bandwidth (in excess of 20 gb/s in ordinary pipelined configuration) and very low random access latency ( 5 ns). the use of very low voltage circuits in the core and 1.8 v or 1.5 v interface voltages allow the speed, power and density performance of s rams. although the sigma ram family of pinouts has been designed to support a number of different common read and write protocol options, not all sigma ram implementations will support all possible protocols. the following timing diagrams provide a quick comparison between read and write protocols options available in the context of the sigma ram standard. this particular data sheet covers the single data rate (non-ddr) sigma ram. c5,d4, d5, d7, d8,k4, k8, k9, t4, t5, t7, t8,u3, u5, u7, u9 nc no connect ? not connected to die (all versions) b5 nc no connect ? not connected to die (x72 version) c7 nc no connect ? not connected to die ( x72/ x36 version s ) a1, a2, b1, b2, b4, b9, c1, c2, c3, c8, d1, d2, e1, e10, f10, f11, g10, g11, h10, h11, j10, j11, l1, l2, m1, m2, n1, n2, p1, p2, r2, r11, t10, t11, u10, u11, v10, v11, w10, w11 nc no connect ? not connected to die (x36/x18 versions) a10, a11, b8, b10, b11, c4, c10, c11, d10, d11, e11, r1, t1, t2, u1, u2, v1, v2, w1, w2 nc no connect ? not connected to die (x18 version) b6 w write input active low e5, e6, e7, g5, g7, j5, j7, l5, l7, n5, n7, r5, r6, r7 v dd core power supply input 1.8 v nominal e3, e4, e8, e9, j3, j4, j8, j9, l3, l4, l8, l9, n3, n4, n8, n9, r3, r4, r8, r9 v ddq output driver power supply input 1.8 v or 1.5 v nominal d3, d9, f3, f4, f5, f7, f8, f9, h3, h4, h5, h7, h8, h9, k5, k7, m3, m4, m5, m7, m8, m9, p3, p4, p5, p7, p8, p9, t3, t9 v ss ground input ? f6 zq output impedance control input ? pin description table pin location symbol description type comments
rev: 1.01 11/2000 7/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 common i/o sigma ram family mode comparison?ew vs. lw vs. dlw the character of the applications for fast synchronous srams in networking systems are extremely diverse. s rams have been developed to address the diverse needs of the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. s rams address each of the bus protocol options commonly found in networking systems. this allows the s ram to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older srams, like the pipelined synchronous burst sram, as well as with new chip sets and asic?s that employ the echo clocks and realize the full potential of the s rams. early write---flow through read late write---flow through read dq early write---pipelined read late write---pipelined read double late write---pipelined read cq qa db qc dd d e f w r w control r w r address a b c df ck cq w control x x w ck qd address df qe a qa dc qa r d dd r db qa qc dd d e f w r w control r w r ck address a b cq f a address b qa c d e w df qd dc w e control dq ck address r x r x c f control r x x w r r b c qe dq ck qe a b c d e f
rev: 1.01 11/2000 8/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 common i/o sigma ram family mode comparison?lw vs. ddr all address , data and control inputs (with the exception of g , pe2, pe3, and the mode pins, m2?m4) are synchronized to rising clock edges. read and write operations must be initiated with the advance/ load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting all three of the chip enable inputs ( e1 , e2, and e3). deassertion of any one of the enable inputs will deactivate the device. it should be noted that only deactivation of the ram via e2 and/or e3 deactivates the echo clocks, cq1?cqn. mode selection truth table standard m2 m3 m4 function analogous to... in this data sheet? 0 0 0 early write, flow through read flow through burst ram yes 0 0 1 late write, flow through read flow through nbt sram & flow through late write sram yes 0 1 0 rfu n/a 0 1 1 ddr double data rate sram no 1 0 0 early write, pipelined read pipelined burst ram yes 1 0 1 double late write, pipelined read pipelined nbt sram yes 1 1 0 late write, pipelined read pipelined late write sram yes 1 1 1 rfu ? n/a late write---pipelined read df cq w control x x w ck qd address qa dc r r a b c d e f double data rate write---double data rate read cq ck address a b c d e f r x w control r x w df0 qa0 qa1 dc1 dc0 qd0 qd1
rev: 1.01 11/2000 9/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 read operations flow through read a flow through read cycle sends data to the output drivers immediately after the address and read command are captured in the input registers. the main clock input, ck, need not ever fire again for data to be driven out. normally, flow through mode is employed in situations where the latency of the ram (the flow through tkhqv) is appreciably shorter than the bus frequency of the application. read deselect write read hi-z read d access key e f ck address a xx /e 1 /w dq c qe dc qa qd sigma early write with flow through read f /e 1 qe db /w dq qa dd qc read d e ck address a b access read write read key hi-z c write sigma late write with flow through read
rev: 1.01 11/2000 10/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 pipelined read read operation is initiated when the following conditions are satisfied at the rising edge of clock: all three chip enables ( e1 , e2, and e3 ) are active, the write enable input signal ( w ) is deasserted high, and adv is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determ ines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the next ri sing edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operations write operation occurs when the following conditions are satisfied at the rising edge of clock: all three chip enables ( e1 , e2, and e3 ) are active and the write enable input signal ( w ) is asserted low. early write the classic ?pb? (pipelined burst) srams employed the ?early write? protocol. this is to say that address, control (the write command), and data in are all required on the same clock edge. /e 1 a dq dd qa write read ck address read deselect deselect f xx xx e d key hi-z access /w cq sigma early write with pipelined read
rev: 1.01 11/2000 11/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 . late write in late write mode the ram requires data in one rising clock edge later than the edge used to load address and control. late write protocol has been employed on srams designed for risc processor l2 cache applications and in flow through mode nbt srams. double late write double late write means that data in is required on the third rising edge of clock. double late write is used to implement pipeline mode nbt srams. read deselect write key qd qa dc read read c d e f access ck address a xx /e 1 /w dq cq hi-z sigma late write with pipelined read
rev: 1.01 11/2000 12/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 byte write control the byte write enable inputs ( b x ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. byte write truth table function w b a b b b c b d read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h dd read write read write read c d f e ck address a b /e 1 /w dq qa cq key qc hi-z access db sigma double late write with pipelined read
rev: 1.01 11/2000 13/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 special functions burst cycles although s rams can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in both late write flow through and double late write pipelined modes, multiple back-to-back reads or writes may also be performed. s rams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. the adv contr ol pin, when driven high, commands the sram to advance the internal address counter and use the counter generated address to read or write the sram. the starting address for the first cycle in a burst cycle series is loaded into the sram by driving the adv p in low, into load mode. da db de da dc f /e 1 write b c d adv non-write write write ck address a e write cq /ba /bb dqa0-dqa8 dqb0-dqb8 byte write control example with x18 sigma late write ram
rev: 1.01 11/2000 14/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 sigma pipelined burst reads with counter wrap-around internal address a2 a3 a0 a1 a2 cq dq qa2 qa3 qa1 counter wraps /e 1 adv a2 xx xx qa0 /w continue ck xx xx read continue continue continue external address d1 d2 xx counter wraps xx a2 cq continue /e 1 adv dq d2 continue ck address a2 xx xx xx continue continue write d0 /w a1 a2 a3 a0 d3 internal addres sigma late write sram burst writes with counter wrap-around
rev: 1.01 11/2000 15/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. sigma rams always count in linear burst order. linear burst order notes: 1. the burst counter wraps to initial state on the 5th rising edge of clock. output enable bus control although the ram is usually more easily operated in an entirely synchronous mode, a single asynchronous output enable pin, g , is provided. g high overrides all other controls and deselects the output drivers, forcing the drivers into a high impedance state. g low returns the ram to normal synchronous control. echo clock s rams feature echo clocks, cq1,cq2, cq 1, and cq2 that track the performance of the output drivers. the echo clocks are delayed copies of the main ram clock, ck. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the echo clocks are designed to fire with the rest of the data output drivers. sigma rams provide both in-phase, or true, echo clock outputs (cq1 and cq2) and inverted echo clock outputs ( cq1 and cq2 ). a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 read c d e read read /e 1 ck address a b read read adv qd cq /g dq qa qb qc output enable control
rev: 1.01 11/2000 16/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. programmable enables s rams feature two user-programmable chip enable inputs, e2 and e3. the sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, pe2 and pe3. for example, if pe2 is held at v dd , e2 functions as an active high enable. if pe2 is held to v ss , e2 functions as an active low chip enable input. programmability of e2 and e3 allows four banks of depth expansion to be accomplished with no additional logic. by programming the enable inputs of four s rams in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four s rams can be made to look like one larger ram to the system. example four bank depth expansion schematic a ck e1 e2 e3 w a 0 ?a n ck w dq 0 ?dq n bank 0 bank 1 bank 2 bank 3 bank enable truth table ep2 ep3 e2 e3 bank 0 v ss v ss active low active low bank 1 v ss v dd active low active high bank 2 v dd v ss active high active low bank 3 v dd v dd active high active high e1 a n ? 1 a n a 0 ?a n ? 2 a n ? 1 a n a 0 ?a n ? 2 a n ? 1 a n a 0 ?a n ? 2 a n ? 1 a n a 0 ?a n ? 2 dq a ck e2 e3 w dq a ck e2 e3 w dq a ck e2 e3 w dq e1 e1 e1 cq cq cq cq cq
rev: 1.01 11/2000 17/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. in some applications it may be appropriate to pause between banks; to deselect both rams with e1 before resuming read operations. an e1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. although the following drawing illustrates a e1 read pause upon switching from bank 1 to bank 2, a write to bank 2 would have the same effect, causing the ram in bank 2 to issue at least one clock before it is needed. echo clock control in two banks of sigma pipelined srams note: e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false. qd cq bank 1 cq bank 2 dq bank 2 qb cq1 + cq2 qc address a b /e 1 /e2 bank 1 e2 bank 2 dq bank 1 qa f d e c read read read ck read read
rev: 1.01 11/2000 18/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 . flxdrive? output driver impedance control the zq pin allows selection between s ram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point applications. see ?output driver characteristics? on page31 for details. pipelined read bank switch with e1 deselect note: e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false. qd qc cq bank 1 cq1 + cq2 cq bank 2 dq bank 2 /e 1 /e2 bank 1 e2 bank 2 dq bank 1 qa address a xx f d e c read read read ck read no op
rev: 1.01 11/2000 19/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 s s ram synchronous truth table ( g low) previous cycle input type e 1 e adv w bx next cycle address dq cq notes n/a d h t l x x deselect cycle none hi-z q ? deselect c x x h x x deselect cycle, continue next hi-z q ? n/a dx x f l x x bank deselect cycle none hi-z hi-z 2 bank deselect c x x h x x bank deselect cycle, continue next hi-z hi-z ? n/a r l t l h x read cycle, begin burst external q q 2 read c x x h x x read cycle, continue burst next q q ? n/a w l t l l t write cycle, begin burst external d q 2, 3 n/a w l t l l f non-write cycle, begin burst external hi-z q 2, 3, 4 write c x x h x t write cycle, continue burst next d q 3, 5, 6 write c x x h x f non-write cycle, continue burst next hi-z q 3, 4, 5, 6 notes: 1. x = don?t care, h = high, l = low 2. e = t (true) if e2 = 1 and e3 = 0; e = f (false) if e2 = 0 or e3 = 1 3. bx = f (false) if all byte write enable pins are high. bx = t (true) if any one byte write enable pin is low. 4. in nbt rams, an active cycle that starts with w = 0 but all bx = false (high) is a write cycle (dq?s hi-z) but no data is written. 5. the byte write enable pins are only evaluated in a continue cycle if the previous cycle was a write. rev. 5
rev: 1.01 11/2000 20/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 read/write control state diagram deselect new read new write burst read burst write w r c r c w d d c c w r d c w r d d current state (n) next state (n + 1) transition ? input command code key note w, r, c and d represent input command codes as indicated in the synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state & next state definition for read /write control state diagram w r
rev: 1.01 11/2000 21/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recommended operating conditions. exposure to conditions exceeding the recommended operating conditions, for an extended period of time, may affect reliability of this component. recommended operating conditions absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.5 v v ddq voltage in v ddq pins ?0.5 to v dd v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 1.7 1.8 1.95 v 1.8 v i/o supply voltage v ddq 1.7 1.8 v dd v 1 1.5 v i/o supply voltage v ddq 1.4 1.5 1.6 v v 1 ambient temperature (commercial range versions) t a 0 25 70 c 2 ambient temperature (industrial range versions) t a ?40 25 85 c 2 notes: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. most speed grades and configurations of this device are of f ered in both commercial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evalu- ated for worst case in the temperature range marked on the device.
rev: 1.01 11/2000 22/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 note: this parameter is sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. temperature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 cmos i/o dc input characteristics parameter symbol min. typ. max. unit notes cmos input high voltage v ih 0.65 * v ddq ? v dd + 0.3 v 2 cmos input low voltage v il ?0.3 ? 0.35 * v ddq v 2 note: for devices supplied with cmos input buffers. compatible with both 1.8 v and 1.5 v i/o drivers. capacitance (t a = 25 o c , f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja tbd c/w 1,2 junction to ambient (at 200 lfm) four r q ja tbd c/w 1,2 junction to case (top) n/a r q jc tbd c/w 3 20% tkc v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 1.0 v 50% v dd v il
rev: 1.01 11/2000 23/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown unless otherwise noted. ac test load diagrams ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua ? mode pin input current i in m v dd 3 v in 3 v il 0v v in v il ?100 ua ?2 ua 2 ua 2 ua ? output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua ? selectable impedance output driver dc electrical characteristics parameter symbol test conditions min. max notes low drive output high voltage v ohl i ohl = ?4 ma v ddq ? 0.4 v ? 1 low drive output low voltage v oll i oll = 4 ma ? 0.4 v 1 high drive output high voltage v ohh i ohh = ?8 ma v ddq ? 0.4 v ? 2 high drive output low voltage v olh i olh = 8 ma ? 0.4 v 2 dq vt = v ddq /2 50 w ac test load a dq ac test load b 5 pf
rev: 1.01 11/2000 24/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 operating currents parameter test conditions symbol -333 0c to 70c ?40c to +85c operating current e1 v il max. tkhkh 3 tkhkh min. g 3 v ih all other inputs v il 3 v in 3 v ih i dd p pipeline tbd ma tbd ma i dd f flow-through tbd ma tbd ma bank deselect current e2 or e3 false tkhkh 3 tkhkh min. g 3 v ih all other inputs v il 3 v in 3 v ih i sb1 pipeline tbd ma tbd ma i sb1 flow-through tbd ma tbd ma chip disable current e1 3 v ih min. tkhkh 3 tkhkh min. g 3 v ih all other inputs v il 3 v in 3 v ih i sb2 pipeline tbd ma tbd ma i sb2 flow-through tbd ma tbd ma cmos deselect current device deselected all inputs v ss + 0.10 v 3 v in 3 v dd ? 0.10 v i dd3 pipeline tbd ma tbd ma i dd3 flow-through tbd ma tbd ma
rev: 1.01 11/2000 25/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 ac electrical characteristics parameter symbol -333 -300 -275 -250 unit notes min max min max min max min max pipeline read clock cycle time tkhkh 3.0 ? 3.3 ? 3.6 ? 4.0 ? ns ? clock high to output valid tkhqv 1.6 1.8 1.9 2.1 ns ? clock high to output in high-z tkhqz 0.5 1.6 0.5 1.8 0.5 1.9 0.5 2.1 ns 1 clock high to output invalid tkhqx 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns ? clock high to output in low-z tkhqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 1 clock high to echo clock low-z tkhcx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 2, 4 clock high to echo clock high tkhch 0.5 1.5 0.5 1.7 0.5 1.8 0.5 2.0 ns 4 clock low to echo clock low tklcl 0.5 1.7 0.5 1.9 0.5 2.0 0.5 2.3 ns 4 output invalid to echo clock high tchqx ? -0.5 ? -0.6 ? -0.6 ? -0.7 ns 2 echo clock high to output valid tchqv ? 0.5 ? 0.6 ? 0.6 ? 0.7 ns 2 clock high to echo clock high-z tkhcz 0.5 1.5 0.5 1.7 0.5 1.8 0.5 2.0 ns 1, 2 flow through read clock cycle time tkhkh 7.0 ? 7.7 ? 8.4 ? 9.3 ? ns ? clock high to output valid tkhqv 5.0 ? 5.5 ? 6.0 ? 6.7 ns ? clock high to output in high-z tkhqz 1.0 5.0 1.0 5.5 1.0 6.0 1.0 6.7 ns 1 clock high to output invalid tkhqx 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns ? clock high to output in low-z tkhqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 1 clock high time tkhkl 1.2 ? 1.3 ? 1.4 ? 1.6 ? ns ? clock low time tklkh 1.2 ? 1.3 ? 1.4 ? 1.6 ? ns ? address valid to clock high tavkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to address don?t care tkhax 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? enable valid to clock high tevkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to enable don?t care tkhex 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? write valid to clock high twvkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to write don?t care tkhwx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? byte write valid to clock high tbvkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to byte write don?t care tkhbx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? data in valid to clock high tdvkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to data in don?t care tkhdx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1. 4. tested using ac test load b
rev: 1.01 11/2000 26/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 adv valid to clock high tadvvkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to adv don?t care tkhadvx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? g to output valid tglqv ? 3.0 ? 3.3 ? 3.6 ? 4.0 ns ? g to output in low-z tglqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 1 g to output in high-z tghqz ? 3.0 ? 3.3 ? 3.6 ? 4.0 ns 1 parameter symbol -333 -300 -275 -250 unit notes min max min max min max min max notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1. 4. tested using ac test load b
rev: 1.01 11/2000 27/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 timing parameter key?read cycle timing tkhqx1 tkhqv tkhqx tkhqz tkhqx1 tkhqv tavkh tkhax tkhqx tkhqz tkhch ck a dq (flow through) dq (pipelined) tkhkh tklkh tkhkl a b c qa qb qa cq tchqv tchqx tkhcx1 tklcl tkhcz = cq high z
rev: 1.01 11/2000 28/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 timing parameter key?control and data in timing jtag port operation overview the jtag port on this ram operates in a manner consistent with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag), but does not implement all of the functions required for 1149.1 compliance. unlike jtag implementations that have been common among sram vendors for the last several years, this implementation does offer a form of extest, known as clock assisted extest, reducing or eliminating the ?hand coding? that has been required to overcome the test program compiler errors caused by previous non-compliant implementations. tkhnx tnvkh tavkh tkhax ck a a b c e1 , e2, e3, w , b n , adv dq (data in) tkhdx tdvkh da tkhdx tdvkh da tkhdx tdvkh da early write late write double late write dq (data in) dq (data in) note: tnvkh = tevkh, twvkh, tbvkh, etc. and tkhnx = tkhex, tkhwx, tkhbx, etc. db dc db
rev: 1.01 11/2000 29/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to v dd . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as tap registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle , or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed thr ough the ram?s jtag port to another device in the scan chain with as little delay as possible. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while t ms is held high for five rising edges of tck. the tap controller is also reset automaticly at power-up.
rev: 1.01 11/2000 30/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 boundary scan register boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between th e device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be used to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code p r e s e n c e r e g i s t e r bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x09 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.01 11/2000 31/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990?the standard (public) instructions, and device specifi c (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1- compliant because some of the mandatory instructions are uniquely implemented. the tap on this device may be used to monitor all input and i/o pads, but cannot be used to load address, data or control signals into the ram or to preload the i/o buffers.t his device will not perform intest or the preload portion of the sample/preload command. when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded wit h 01. when the controller is moved to the shift-ir state, the instruction register is placed between tdi and tdo. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register, the bypass register is placed between tdi and tdo. this occur s when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing o f other devices select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1
rev: 1.01 11/2000 32/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruc - tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bou ndary scan register. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable in puts will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the tap?s i nput data capture set-up plus hold time (tts plus tth ). the ram?s clock inputs need not be paused for any other tap operation except capt uring the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan registe r between the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the update-dr state with the sample/preload instruction loaded in the instruction register has the same effect as the pause-dr com- mand. this functionality is not standard 1149.1-compliant. extest (extest-a) extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length i t may be in the device, is loaded with all logic 0s. the extest implementation in this device does not, without further user intervention, a ctually move the contents of the scan chain onto the ram?s output pins. therefore this device is not strictly 1149.1-compliant. nevertheless, this ram?s tap does respond to an all 0s instruction, extest (000), by overriding the ram?s control inputs and activating the data i/o out put drivers. the ram?s main clock (ck) may then be used to transfer boundary scan register contents associated with each i/o from the scan re gister to the ram?s output drivers and onto the i/o pins. a single ck transition is sufficient to transfer the data, but more transitio ns will do no harm. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z ) and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction.
rev: 1.01 11/2000 33/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 jtag tap instruction set summary instruction code description notes extest-a 000 places the boundary scan register between tdi and tdo. this ram implements an clock assisted extest function. *not 1149.1 compliant * 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all data and clock output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this ram does not implement 1149.1 preload function. *not 1149.1 compliant * 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input high voltage v iht 0.65 * v dd v dd +0.3 v 1 test port input low voltage v ilt ?0.3 0.35 * v dd v 1 tms, tck and tdi input leakage current i in th ?100 2 ua 2 tms, tck and tdi input leakage current i in tl ?2 2 ua 3 tdo output leakage current i olt ?2 2 ua 4 test port output high voltage v oht v ddq ? 100 mv ? v 5, 6 test port output low voltage v olt ? 100 mv v 7 notes: 1. input under/overshoot voltage must be ?1 v < vi < v dd + 1 v with a pulse width not to exceed 20% ttkc. 2. v dd 3 v in 3 v il 3. 0 v v in v il 4. output disable, v out = 0 to v dd 5. the tdo output driver is served by the v dd supply. 6. i oh = ?100 ua 7. i ol = +100 ua
rev: 1.01 11/2000 34/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 jtag port timing diagram jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 20 ? ns tck low to tdo valid ttkq ? 10 ns tck high pulse width ttkh 10 ? ns tck low pulse width ttkl 10 ? ns tdi & tms set up time tts 5 ? ns tdi & tms hold time tth 5 ? ns notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 200 mv input low level 200 mv input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 dq v t = v dd /2 50 w jtag port ac test load ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.01 11/2000 35/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 output driver characteristics tbd
rev: 1.01 11/2000 36/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 package dimensions?209-bump bga 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min. typ. max. units a ? ? 1.7 mm a1 0.40 0.50 0.60 mm a2 0.31 0.36 0.38 mm b 0.50 0.60 0.70 mm d 21.9 22.0 22.1 mm d1 ? 18.0 (bsc) ? mm e 13.9 14.0 14.1 mm e1 ? 10.0 (bsc) ? mm e ? 1.00 (bsc) ? mm ddd ? 0.15 ? mm rev 1.2 a a1 a2 ? b e e e e 1 d1 d ddd bottom view side view
rev: 1.01 11/2000 37/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 ordering information?gsi sigma ram org part number 1 type package speed 2 (mhz /ns ) t a 3 256k x 72 gs817 0 s 72b-333 common i/o s ram 1 mm pitch, 209-pin bga 333/5 c 256k x 72 gs817 0 s 72b-300 common i/o s ram 1 mm pitch, 209-pin bga 300/5.5 c 256k x 72 gs817 0 s 72b-275 common i/o s ram 1 mm pitch, 209-pin bga 275/6 c 256k x 72 gs817 0 s 72b-250 common i/o s ram 1 mm pitch, 209-pin bga 250/6.7 c 256k x 72 gs817 0 s 72b-333i common i/o s ram 1 mm pitch, 209 pin bga 333/5 i 256k x 72 gs817 0 s 72b-300i common i/o s ram 1 mm pitch, 209-pin bga 300/5.5 i 256k x 72 gs817 0 s 72b-275i common i/o s ram 1 mm pitch, 209-pin bga 275/6 i 256k x 72 gs817 0 s 72b-250i common i/o s ram 1 mm pitch, 209-pin bga 250/6.7 i 512k x 36 gs817 0 s 36b-333 common i/o s ram 1 mm pitch, 209-pin bga 333 /5 c 512k x 36 gs817 0 s 36b-300 common i/o s ram 1 mm pitch, 209-pin bga 300 /5.5 c 512k x 36 gs817 0 s 36b-275 common i/o s ram 1 mm pitch, 209-pin bga 275 /6 c 512k x 36 gs817 0 s 36b-250 common i/o s ram 1 mm pitch, 209-pin bga 250 /6.7 c 512k x 36 gs817 0 s 36b-333i common i/o s ram 1 mm pitch, 209-pin bga 333 /5 i 512k x 36 gs817 0 s 36b-300i common i/o s ram 1 mm pitch, 209-pin bga 300 /5.5 i 512k x 36 gs817 0 s 36b-275i common i/o s ram 1 mm pitch, 209-pin bga 275 /6 i 512k x 36 gs817 0 s 36b-250i common i/o s ram 1 mm pitch, 209-pin bga 250 /6.7 i 1mx 18 gs817 0 s 18b-333 common i/o s ram 1 mm pitch, 209-pin bga 333 /5 c 1mx 18 gs817 0 s 18b-300 common i/o s ram 1 mm pitch, 209-pin bga 300 /5.5 c 1mx 18 gs817 0 s 18b-275 common i/o s ram 1 mm pitch, 209-pin bga 275 /6 c 1mx 18 gs817 0 s 18b-250 common i/o s ram 1 mm pitch, 209-pin bga 250 /6.7 c 1mx 18 gs817 0 s 18b-333i common i/o s ram 1 mm pitch, 209-pin bga 333 /5 i 1mx 18 gs817 0 s 18b-300i common i/o s ram 1 mm pitch, 209-pin bga 300 /5.5 i 1mx 18 gs817 0 s 18b-275i common i/o s ram 1 mm pitch, 209-pin bga 275 /6 i 1mx 18 gs817 0 s 18b-250i common i/o s ram 1 mm pitch, 209-pin bga 250 /6.7 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs817x72b-300t. 2. the speed column indicates the cycle frequency (mhz) of the device in pipelined mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range.
rev: 1.01 11/2000 38/38 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8170 s 18/36 /72 b-333/300/275/250 revision history rev. code: old; new types of changes format of content revisions 8170s183672_r1; 8170s183672_r1_01 format updated format to comply with technical publications standards

▲Up To Search▲

Price & Availability of GS8170S18

	To Download GS8170S18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .